Publications from the VLSI Group (as of August'07)

  1. A. Bhatt , N.Choudhuri and S.Chouksey “A Novel Algorithm for Software Scheduling and Methods to Reduce Stalls in RISC Pipelined Processor,” Malaysia Region 10 Contest, 2004.
  2. A. Bhatt and M. Desai “Reconfiguration in SOC with Programmable Interconnect,” VLSI Design and Test (VDAT 2003), 2003.
  3. A. Bhatt, C. Sachdeva; M.Desai,; N Choudhuri ; S.Chouksey; Y. Bansal,; T. Ahmed; and T. Abbasi “32 bit RISC Pipelined Processor,” ICON Cadence India Newsletter, February 2005.
  4. A.Gautam, K. Pratyush Aditya, A.Geeta Madhuri, Priya Khandelwal, Meghana Desai, "VLSI Implementation of JPEG2000" , CDN (Cadence Designers Network) LIVE! Bangalore, 2005.

  5. A.Gautam, A.Geeta Madhuri,  P. Khandelwal, K. Pratyush Aditya, Meghana Desai, "Novel Architecture of EBC for JPEG2000" ,vlsid, pp. 530-533,  19th International Conference on VLSI Design held jointly  with 5th International Conference on Embedded Systems Design (VLSID'06),  2006.
  6. H. K. Kapoor and M. B. Josephs (2005) "Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation". In Proceedings of the 5th International Conference on Application of Concurrency to System Design (ACSD), pp.58-67, IEEE Computer Society Press.
  7. H. K. Kapoor, M. B. Josephs and D. P. Furey (2006) "Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments". In the Third Special Issue on Application of Concurrency to System Design of the Journal Fundamenta Informaticae, 70(1-2):21-48, January 2006, IOS Press, Netherlands.
  8. H. K. Kapoor and M. B. Josephs (2004) "Modelling and Verification of Delay-Insensitive Circuits using CCS and the Concurrency Workbench ".
    In Information Processing Letters 89(6):293-296, March 2004, Elsevier.

  9. M. Rastogi, D. , Nagchoudhuri, and C. Parikh; “Quadratic Phase Coupling in ECG Signals,” Sensors and the International Conference on new Techniques in Pharmaceutical and Biomedical Research, 2005 Asian Conference, Kualalampur, Malaysia, 5th – 7th Sept. 2005, pp. 74-77.
  10. N. Khera, Anil K. Roy and Chetan Parikh, "Low Power, High Bit Rate CMOS Driver for VCSEL used in Free Space Optical Interconnect", Proc. IEEE/LEOS Summer Topical Conference, San Diego, 2005.
  11. N.Vinod Reddy, Prabhat Saraswat “A Novel Sense Resistor Based Instantaneous Current Measuring Approach for Instruction Level Power Modeling of Embedded Systems “ presented at National Conference on Embedded Systems 2006, India.
  12. S. Bharadwaj and S. Goyal “Custom Design of Indian Rail road Crossing Controller” got 2nd prize in Eclectica PEC feb 9-12 2006, Technical paper presentation.

  13. S. Bharadwaj, N. Vinod Reddy and Ravi Shekhar “ A 3ns 16X16 Pipelined, Modified Booth Encoded Multiplier for High Speed DSP” got published in Eclectica proceedings PEC feb 9-12 2006.
  14. S.Mohanty " Design of a Low Power MAC unit using custom based approach" , National Conference on Communication technology
  15. Sethi A. , Arora S., and Ballaney A., "Frequency Domain Analysis of ECG Signals using Auto-Associative Neural Networks (AANN)", IEEE International Conference on Biomedical and Pharmaceutical Engineering 2006.
  16. G. Kaushik "current feedback amplifier design for fast data transmission systems" selected for poster presentation in ECLECTICA '06, technical festival PEC Chandigarh.
  17. J. B. Bensal" A Low Voltage Low Power High Swing Operational Amplifier for High Speed Analog to Digital Converters ", Proc. of National conference on Trends in Industry and Commercial Applications of Electronics(TICAE-2006), Sathyabhama University, Chennai, March 22nd –24th 2006.
  18. Malav Shah, "Scan Based BIST Test Scheme" -- 1st prize and published in proceedings of Eclectica '06 Technical paper presentation at PEC Feb 9-12, 2006.
  19. Malav Shah, "Low Power Testing Scheme" was selected at IDEAZ paper presentation in Cognizance '06 at IIT Roorkee
  20. G.Kaushik, "High Speed Receiver Amplifier Design Using CMOS Current Feedback Amplifier & Current Conveyors", proceedings, 10th WSEAS International Conference on CIRCUITS, Athens, Greece, July 10-15, 2006 (also proposed for WSEAS journal publication).
  21. D. Nagchoudhuri et al, Analysis of an ECG Signal by Trispectrum Technique, Eurasip Journal of Applied Signal Processing(Special Issue on Nonlinear Signal and Image Processing).
  22. D. Nagchoudhuri et al, Phase Correlations in Human EEG Signal : A Case Study, IEEE International Workshop on Electronic Design  Test  and Applications (DELTA) 2004.
  23. Gaurav Arora,Abhishek Sharma,D.Nagchoudhuri,M.Balakrishnan: ADOPT: An Approach to Activity Based Delay Optimization. VLSI Design 2005: 411-416
  24. "Mukul Milind Ojha,Arun Kumar Anand,G. S. Visweswaran,D. Nagchoudhuri: A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip.VLSI Design 2005: 828-831
  25. Gagandeep S. Sandha,Pawan K.Singh,C. Pradeep Kumar,D. Nagchoudhuri: Quantitative Model for Thermal Behaviour of an Analog Integrated Circuit."VLSI Design 2004:623-626
  26. Gagandeep S. Sandha, Pawan K. Singh, Neha Oberoi, D. Nagchoudhuri: Phase Correlations in Human EEG Signal: A Case Study. DELTA 2004: 41-46
  27. Sahil M. Bansal, Punjab Engineering College and D.Nagchaudhuri, DA-IICT Minimization in Variation of Output Characteristics of a SOI MOS Due to Self Heating. VLSI Design and Test Symposium 2004.
  28. H. K. Kapoor (2006) " Formal Modelling and Verification of an Asynchronous DLX Pipeline ".In Proceedings of the 4th IEEE International Conference on Software Engineering and Formal Methods (SEFM) , pp. 118-127, IEEE Computer Society Press.
  29. H. K. Kapoor and M. B. Josephs (2005)" Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation ".In Proceedings of the 5th International Conference on Application of Concurrency to System Design (ACSD) , pp. 58-67, IEEE Computer Society Press.
  30. H. K. Kapoor, M. B. Josephs and D. P. Furey (2004)
    " Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments ".In Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD) , pp. 89-98, IEEE Computer Society Press. (Selected for a special issue of the Journal Fundamenta Informaticae, IOS Press, Netherlands.
  31. H. K. Kapoor and M. B. Josephs (2004)"Decomposing Specifications with Concurrent Outputs to Resolve State Coding Conflicts in Asynchronous Logic Synthesis ".In Proceedings of 41st Design Automation Conference (DAC) , pp. 830-833, ACM.
  32. A. Ray and C. D. Parikh, "A 2.4 GHz low-voltage CMOS low noise amplifier with 32 dB gain," VLSI Design and Test Symposium, 2007, Kolkata.
  33. N. Rao and C. D. Parikh, "Low-power High Slew-rate Adaptive Biasing Circuit for CMOS Amplifiers," VLSI Design and Test Symposium, 2007, Kolkata.
  34. Shagun Bajoria, Vineet Kumar Singh, Raju Kunde and Chetan D. Parikh, "Low Power High Bandwidth Amplifier with RC Miller and Gain Enhanced Feedforward Compensation," Proc. International Symposium on Low Power Electronics and Design, ISLPED-2008, Bangalore, August, 2008, pp. 193-196.
  35. Amit K. Gupta and Chetan D. Parikh, "A CMOS Comparator Circuit Optimized for Power-Delay Product and Input-Output Isolation," in Proceedings of 12th IEEE VLSI Design and Test Symposium, VDAT 2008, Bangalore, Aug., 2008, pp. 10-17.
  36. Shekhar Gupta, Kishore Yalamanchili “Parallel DCT Computation with Network on Chip and Analysis on Mesh and Star Topologies” accepted as poster paper in International Conference on Emerging Trends in Engineering & Technology (ICETET-08), Nagpur(India), July 2008
  37. Shekhar Gupta, Kishore Yalamanchili, Divya Macharla “Topology design using Network Simulator (NS2) for parallel FFT computation with Network on chip” in Proceedings of National Conference on VLSI and Communication (NCVCom-08) Kottaym, Kerala (India) March 2008, pp 207-209.
  38. Dubey, Rahul “Introduction to Embedded System Design Using Field Programmable Gate Arrays,” Berlin: Springer, 2008.
  39. Bajoria, Shagun; Singh, vineet Kumar; Kunde, Raju and Parikh, Chetan“Low power high bandwidth aplifier with RC miller and gain enchanced feedforward compensation; in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED 2008), Bangalore, Aug. 11-13, 2008. pp. 193-196.
  40. BGupta, Amit Kumar and Parikh, Chetan“A CMOS comparator circuit optimized for power-delay product and input-output isolation; in Proceedings of 12th IEEE VLSI design and Test Symposium (VDAT 2008), Bangalore, Jul. 23-26, 2008. pp. 10-17.
  41. BMillman, Jacob; Halkias, Christos and Parikh, Chetan D“Millman's Integrated Electronics; New Delhi: Tata McGraw-Hill, 2009.
  42. Lodha, Nupur; Rai, Nivesh; Dubey, Rahul and Venkataraman, Hrishikesh.“Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor ; in Proceedings of Third International Conference on Information Systems, Technology and Management (ICISTM-2009), Ghaziabad, Mar. 12-13, 2009. pp. 197-207.
  43. Ranjith, P.; Mandal, Sushanta K. and Nagchoudhuri, Dipankar“Ranjith, P.;An efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry-save multiplier; in Proceedings of Fourth International Conference on Computers & Devices for Communication, Kolkata, India, Dec. 14-16, 2009, pp. 1-4.
  44. Hammerstrom, Dan and Zaveri, Mazad S“CMOL/CMOS implementations of bayesian inference engine: Digital and mixed-signal architectures and performance/price - a hardware design space exploration; in CMOS Processors and Memories, Krzysztof Iniewski Ed. Berlin: Springer, 2010.
  45. Zaveri, Mazad S. and Hammerstrom, Dan“CMOL/CMOS implementations of bayesian polytree inference: digital & mixed-signal architectures and performance/price;IEEE Transactions on Nanotechnology, vol. 9, no. 2, pp. 194-211, Mar. 2010.
  46. Salimath, Arunkumar; Debnath, Chandrajit; Chatterjee, Kallol; Mandal, Sushanta K“A 6 bit 800MHz TIADC based on successive approximation in 65nm standard CMOS process;in Proceedings of 23rd International Conference on VLSI Design, Bangalore, IN, Jan. 3-7, 2010, pp. 312-317.
  47. Purushothaman, K. and Parikh, Chetan D“Design of static latch-based comparators using power constrained optimization;in Proceedings of 14th IEEE VLSI Design and Test Symposium(VDAT 2010), Chandigarh, Jul. 7-9, 2010.
  48. Zaveri, Mazad S. and Hammerstrom, Dan“Performance/price estimates for cortex-scale hardware: a design space exploration," Neural Networks, 2011. (To appear);
  49. Sen, Subhajit;“Analysis of Tracking Distortion in Bootstrapped gate MOSFET Sample-Hold Circuits and a Method for its Minimization;IETE Journal of Research, Jan.-Feb., 2011.;