M.tech Project Abstracts

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#sort iconStudent NameProject TitleProject GuideAbstract
Abhinav Asthana Design and Synthesis of Asynchronous CircuitsProf. Hemangee Kapoor Abhinav.doc (20 KB)
Aditya VijLow power built in self- test (BIST) architecture for fast multiplier embedded coreProf. D. Nagchoudhuri Aditya.doc (19 KB)
Aseem Verma Design of a Low power high slew rate OPAMPProf. Chetan D. Parikh Aseem_verma.doc (34 KB)
Gaurav KaushikReceiver Amplifier Design For Receiver Unit of Fast DATA Transfer SystemProf. D. NagchoudhuriGaurav_ Kaushik.doc (465 KB)
Jay Kumar Patel Deep Submicron Extractor using probability distributionProf. D. Nagchoudhuri and Mr. Rajendra Pratap, Cadence Design Systems, New Delhi Jay_Patel.doc (10 KB)
Jitendra Babu Bensal A Low Voltage Low Power High Swing Operational Amplifier for High Speed Analog to Digital ConvertersProf. D. Nagchoudhuri Jitendra.doc (48 KB)
Malav ShahScan-Based BIST VLSI Testing (DFT) Scheme for Low Heat Dissipation and Reduced Test Application TimeProf. D. Nagchoudhuri Malav.doc (38 KB)
Manu Tandon Novel architecture of Pipelined ADCProf. Chetan D. Parikh Manu_tandon.doc (20 KB)
Ronak P. Trivedi Low Power and High Speed Sample-and-Hold CircuitProf. D. Nagchoudhuri Ronak.doc (47 KB)
Swaprakash MohantyDesign of a low power, high speed MAC unit using custom based approachProf. D. NagchoudhuriSawprakash_Mohanty.doc (19 KB)
Yogesh Malviya Extremely Low Voltage Rail to Rail Operational Amplifier DesignProf. D. Nagchoudhuri Yogesh_Malviya.doc (1476 KB)
Anuradha Ray A Novel Architecture of a CMOS LNA at 2.4GHz Prof.Chetan D.Parikh anuradha.doc (25 KB)
Mahavir JainBIST architecture for Mixed Signal SystemsProf. D. Nagchoudhuri, Prof. Sushanta Kumar MandalMahavir jain.doc (12 KB)
Neha Khera Design of LASER driver circuit Prof.Chetan D.Parikh neha.doc (25 KB)
Mangesh BhaleraoBuilt-In Self-Test for a Flash Analog to Digital Converter Prof.Chetan D.Parikh mangesh.doc (25 KB)
Divya Aggarwal A Fault Diagnosis Algorithm for a Flash ADC using Oscillation Based Testing Technique Prof.Chetan D.Parikhdivyaagarwal.doc (26 KB)
Narayana Rao Low Power High Slew-Rate Adaptive Biasing Circuit for CMOS Amplifiers Prof.Chetan D.Parikhnarayana.doc (24 KB)
Ram Sahay Singh Implementation of a constant-g m CMOS op-amp input stage using overlapping of transition regions Prof.Chetan D.Parikhramsahay.doc (24 KB)
Marshnil Dave Comparison of single-bit and multi-bit second order sigma-delta modulators Prof.Chetan D.Parikhmarshnil.doc (25 KB)
Amit Kumar Gupta An Optimized CMOS Comparator Design for Analog to Digital Converters Prof.Chetan D.Parikhamit.doc (24 KB)
Divya Dubey Design of Low Voltage High Performance, Wide Bandwidth Current Feedback Amplifier with Complementary Input Pair Prof.Chetan D.Parikhdivyadubey.doc (25 KB)
Maitry Upraity Area Reduction in 8 Bit Binary DAC using Current Multiplication Prof.Chetan D.Parikhmaitry.doc (24 KB)
Raju Kunde A Frequency Compensation Technique For Low Voltage Three Stage Operational Amplifier Prof.Chetan D.Parikhraju.doc (24 KB)
Garima Bajaj Design of Linear adaptive-biased operational amplifier Prof.Chetan D.ParikhGarima.doc (10 KB)
Venkata Raghava Sesha SaiDesign of a wideband low-phase-noise low power voltage controlled oscillator Prof.Chetan D.Parikhsesha sai.doc (24 KB)
Vivek VermaLow-Voltage, Low-Power, High-Dynamic Range, High Band-Width VGAProf.Chetan D.Parikhvivek verma.doc (27 KB)
Bhavi PanchalCurvature Compensated all-CMOS voltage ReferenceProf.Chetan D.ParikhBhavi Panchal.doc (27 KB)
Ch. Uday KumarDesign of a low voltage high linearity mixerProf.Chetan D.ParikhUday Kumar.doc (28 KB)
Akhil RathoreDesign of a CMOS I/O Buffer circuitProf.Chetan D.ParikhAkhil Rathore.doc (27 KB)
R. Ramesh Design of low voltage high performance voltage controlled oscillator Prof. D. Nagchoudhuri ,Prof. Sushanta Mandal ramesh.doc (27 KB)
P. Ranjith Designing of an Efficient Power Clock generation circuit for Complementary Pass-transistor Adiabatic Logic Carry Save MultiplierProf. D. Nagchoudhuri , Prof. Sushanta Mandal Ranjith.doc (27 KB)
Ajay Kumar Sinha A High Speed 512-point FFT Single-Chip Processor ArchitectureProf. D. Nagchoudhuri , Prof. Sushanta Mandal Ajay Kumar Sinha_'.doc (26 KB)
Punam Sen Gupta Design of Low Power and high Speed Decoder for 1Mb MemoryProf. D. Nagchoudhuri Punam Sen Gupta.doc (26 KB)
Navneet Gupta, ASIC Implementation of Discrete Fourier Transform Processing ModuleRahul Dubey,Vaibhav_Agarwal.doc (27 KB)
Vishal BhattLow Power Microprocessor DesignProf.Rahul Dubeyvishal_Bhatt.doc (26 KB)
Vaibhav AgarwalASIC Implementation of a Pipelined Bitrapezoidal Architecture For Discrete Covariance Kalman FilterProf. Rahul Dubey,Vaibhav_Agarwal.doc (27 KB)